This invention relates generally to design automation of Very Large Integrated Circuits (VLSI), and more particularly to multiple voltage threshold timing analysis of digital integrated circuits.
Timing and noise analysis are key verification steps in every design flow for ultra deep sub-micron VLSI circuits. In these applications a pre-characterized high level model of a cell such as a logic gate loaded by an interconnect circuit is analyzed in order to determine delays through the various logic stages. Traditionally logic gates were modeled by ideal delays and their driving properties by simple Thevenin voltage sources. The signals were represented as idealized ramp shaped voltage waveforms. This approach has proven to be insufficiently accurate for timing and noise analysis purposes for chips implemented in the newest technologies. The main source of inaccuracy is the fact that the pre-characterization process can be practically performed only in terms of purely capacitive loads while the reality of the modern VLSI interconnect drifts further and further away from this assumption. On chip wires are highly resistive and even the inductive effects become significant at high frequencies. As a consequence the timing analysis algorithm has the challenge to adapt the pre-characterization data collected with just pure capacitive loading to the reality of RLC loads.
The VLSI industry addressed this challenge mainly by introducing the concept of an effective capacitance that would capture the effect of a resistive-capacitive load. The effective capacitance is a function of two parameters: (1) output voltage waveform of the driving gate and (2) the characteristics of the load, more specifically the driving point admittance of the interconnect. Two gates are considered to be equivalent in terms of calculating effective capacitance if they produce the same output waveform when driving the same load.
There are several approaches that can be used to calculate the effective capacitance. One effective capacitance calculation technique uses a two-piece output waveform that approximates the output waveform of a complementary metal-oxide-semiconductor (CMOS) gate. This technique calculates the effective capacitance by equating the charges at the gate output when using the driving-point admittance of the load and using a single effective capacitance as the load. Average charges for both load models are equated until the gate output voltage reaches the 50% threshold. Another approach uses a table of circuit simulation results and a pair of two-dimensional delay tables to calculate a value for the effective capacitance. In this approach, the effective capacitance is a function of the total capacitance in the π-model (Ctotal), the gate output slew rate, and the Elmore delay of the load. The π-model load is approximated with an effective capacitance such that the output voltage waveforms of the driving cell passes through some critical voltages (e.g., 0.2Vdd and 0.8Vdd) at the same instances in time. In another approach, the effective capacitance is calculated to approximately match both 50% propagation delay and the output transition time. All these approaches which produce just a single number, the effective capacitance, are bound to become inaccurate for the increasingly complicated gate and interconnect models in advanced VLSI technologies.
As a consequence, the recent trend in the industry is to adopt electrically-based driver modeling (e.g., Controlled Current Source Models) within timing and noise analysis engines. Examples are Cadence and Magma's effective current source model (ECSM) and Synopsys' composite current source model (CCS). The ECSM model, for example, represents drivers as controlled current sources dependent on the driving point voltage and a so-called dynamic capacitance: I=fI(V,C). The characterization process for this model is repeated simulations over ranges of ideal voltage ramp input excitations and pure capacitive loads. The results of these simulations are tabulated as driving point transition times as a function of voltage thresholds, and capacitive loads, T=fT(V,C) data. The controlled-current source model I=fI(V,C) model is obtained by fitting to the T=fT(V,C) data. CCS uses a similar characterization style; the main difference is that the characterization data is stored as current (rather than voltage) as a function of time and capacitive load. The two raw characterization data sets are essentially equivalent and can be mapped from one to another.
Both ECSM and CCS modeling imply the transformation of raw modeling data, e.g. T=fT(V,C) into a nonlinear controlled current source device, e.g. I=fI(V,C). This intermediate transformation incurs additional approximations and loss of accuracy. Moreover, these models require a relatively high degree of continuity and smoothness for accurate, reliable, and efficient timing and/or noise analysis.